S1D13A05
QVGA LCD Controller
The S1D13A05 is an LCD solution designed for seamless connection to a wide variety of microprocessors. The S1D13A05 integrates an LCD graphics controller with an embedded 256K byte SRAM display buffer. The LCD controller supports TFT and passive panel types and includes a Hardware Acceleration Engine to greatly improve screen drawing functions.
The S1D13A05 utilizes a guaranteed low-latency CPU architecture that provides support for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data path, write buffer and the Hardware Acceleration Engine provide high performance bandwidth into display memory allowing for fast display updates.
Additionally, products requiring a rotated display can take advantage of the SwivelView™ feature which provides hardware rotation of the display memory transparent to the software application. The S1D13A05 also provides support for Picture-in-Picture (a variable size Overlay window).
The S1D13A05's impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications in embedded markets.
Related Information
| Product Brief v4.2 | 259.7 KB |
| Hardware Specification Rev. 7.8 | 2.04 MB |
| Register Summary Rev 1.0 | 425.57 KB |
| S5U13A05P00C100 Evaluation Board User Manual Rev 1.02 | 762.25 KB |
| S5U13A05B00C Rev 1.0 Evaluation Board User Manual Rev 2.1 | 801.99 KB |
| S5U13A05B00C Design Resources | 104.25 KB |
| Programming Notes And Examples Rev 6.1 | 1.1 MB |
| Sample Code For Programming Notes | 184.13 KB |
| Initialization Source Example | 87.81 KB |
| Win32 Utilities (CFG, PLAY, and VIEW) | 682.88 KB |
| Win32 Utility User Manuals | 273.03 KB |
| Source Code for Win32 Utilities | 270.29 KB |
| Interface Application Notes | 344.85 KB |
| Power Consumption Rev 1.1 | 207.56 KB |
